Abstract: According to the problems of digital down converter based on look-up table, which occupies of a large number of block RAM and hardware multiplier resources, this paper puts forward an efficient and compact CORDIC-DDC architecture for implementation of DDC in FPGA, and the detailed performance analysis is made. Compared to the traditional look-up table implementation, the actual system implementation results show that the multiplier-free method achieves savings of above 60% of the block RAM resources, and increasing 38% of the maximum operating speed.

Key words: software radio, Doppler radar, digital front end, CORDIC-DDC algorithm, FPGA